The chip of a NAND flash memory applied to, for example, an SSD, etc., includes a terminal that outputs a ready/busy signal indicating the state of processing inside the chip. The controller of a NAND flash memory is able to determine the state of processing inside a particular NAND flash memory chip when receiving the ready/busy signal output from the NAND flash memory chip, for example by issuing a status read command. However, issuing status read commands for each individual chip in a NAND flash memory can be time-consuming and affect NAND memory performance.